Professor Robert Wille

Institute for Integrated Circuits 

Johannes Kepler University Linz, Austria

 

 

Robert Wille is a Full Professor at the Johannes Kepler University Linz. He received the Diploma and Dr.-Ing. degrees in computer science from the University of Bremen, Germany, in 2006 and 2009, respectively. He was with the Group of Computer Architecture at the University of Bremen and with the German Research Center for Artificial Intelligence (DFKI). Additionally, he worked as Lecturer at the University of Applied Science in Bremen, Germany, and as visiting professor at the University of Potsdam, Germany, and the Technical University Dresden, Germany. His research interests are in the design of circuits and systems for both conventional and emerging technologies with a focus in the domain of synthesis and verification. Since 2007, he published approx. 200 journal and conference papers in this area and was repeatedly awarded (e.g. with a Best Paper Award at ICCAD in 2013 and FDL in 2010). Besides that, he served Guest Editor for the ACM’s JETC, Springer's LNCS, and the MVLSC. Additionally, he was PC Chair at ISMVL, FDL, and others as well as frequent PC member and track chair for conferences such as ASP-DAC, DAC, DATE, ICCAD, and more.

More information visit: http://www.jku.at/iic/wille

Title: Towards Lightweight Satisfiability Solvers for Self-Verification

 

Dr. Samarjit Chakraborty,

Professor, Chair for real-time computer systems,

Faculty of Electrical Engineering and Information Technology

Technical University of Munich, Germany

 

Samarjit Chakraborty is a Professor of Electrical Engineering at the Technical University of Munich, where the holds the Chair for Real-Time Computer Systems. From 2011 – 2016 he also led a research program on embedded systems design for electric vehicles at the TUM CREATE Centre for Electromobility in Singapore, where he additionally as a Scientific Advisor. Prior to joining TU Munich in 2008, he was an Assistant Professor of Computer Science at the National University of Singapore from 2003 - 2008.  He obtained his Ph.D. in Electrical and Computer Engineering from ETH Zurich in 2003. He works on various aspects of embedded systems and software design and has/had several funded projects from the industry such as from General Motors, Intel, Google, BMW, Bosch, Siemens and Audi, as well as from government funding agencies both in Germany as well as in Singapore. He serves on the editorial boards of the IEEE Transactions on Computers, ACM Transactions on Cyber-Physical Systems, Leibniz Transactions on Embedded Systems, Springer Lecture Notes in Electrical Engineering (LNEE), and the Design Automation for Embedded Systems.

Title: EDA for Cyber-Physical Systems.

Abstract: Over the years, electronic design automation (EDA) has been moving up the design abstraction ladder. Starting from automating tasks like placement, floorplanning and routing in integrated circuits design, EDA now encompasses many system-level design tasks. However, the next challenge facing the EDA is community is to develop methods and also tools for cyber-physical systems (CPS) design. For these systems, physical processes, control algorithms that control these processes, and the computation and communication platforms on which these control algorithms are implemented – are all modelled and designed in a tightly integrated fashion. Currently available EDA methods and tools are not equipped to handle such integrated modeling and design. In this talk we will discuss what are possible ways to address this situation in order to effectively design and validate large scale cyber-physical systems.

 

Dr. Anupan Chattopadhyay,

School of Computer Science and Engineering,

College of Engineering,

Nanyang Technological university, Singapore

 

 

Anupam Chattopadhyay received his B.E. degree from Jadavpur University, India in 2000. He received his MSc. from ALaRI, Switzerland and PhD from RWTH Aachen in 2002 and 2008 respectively. From 2008 to 2009, he worked as a Member of Consulting Staff in CoWare R&D, Noida, India. From 2010 to 2014, he led the MPSoC Architectures Research Group in RWTH Aachen, Germany as a Junior Professor. Since September, 2014, he is appointed as an assistant Professor at the School of Computer Science and Engineering, NTU with honorary adjunct appointment at the School of Physical and Mathematical Sciences, NTU.

Title: The Return of Design Automation.

Abstract: Automation has been a part of diverse industries since the age of industrial revolution, and Semiconductor industry has been no exception. However, the breaking of Dennard scaling, decline of Moore¹s law and advent of new technologies have put the traditional Electronic Design Automation (EDA) in crossroads. In the first part of the talk, I will discuss how several new technologies are offering promising alternatives to CMOS and how they need to be treated with respect, i.e., enhanced design automation flows. In the second part of the talk, I will shift focus on the application perspective. I will argue that the current High-level Synthesis tools need to consider the designer inputs for productivity, efficiency and greater adoption. In this respect, a HLS flow, which is specific to cryptographic primitives will be presented.

 

 

Dr. Writam Banerjee,

Key Laboratory of Microelectronics Devices & Integrated Technology,

Institute of Microelectronics,

Chinese Academy of Sciences (CAS), Beijing, China

 

 

Dr. Writam Banerjee, is an Assistant Professor of Institute of Microelectronics of Chinese Academy of Science (IMECAS) at Beijing since 2014. He is mainly involved with the development and design of ultra-highdensity emerging non-volatile memory technologies. From 2012-2013, Dr. Banerjee held the position of a visiting Scientist at PGI-7, Forschungszentrum Jülich GmbH, Germany, where he led the joint project of Intel Corporation, California and Forschungszentrum Jülich GmbH, Germany. He was engaged for the development of nano-crossbar RRAM devices and integrated with the transistors, in collaboration with IMEC, Belgium. From 2007-2012, Dr. Banerjee has earned Doctor of Philosophy (Ph.D.) degree in Electronic Engineering from the Chang Gung University, Taiwan. He received his M.Sc and B.Sc in Physics from Vidyasagar University, West Bengal, India. Dr. Banerjee have authored and co-authored over 30 publications in reputed international journals (e.g. Advanced Materials, Small, Nanoscale, Scientific Reports, IEEE Electron Device Letter etc.), over 50 publications in conference proceedings (including IEEE International Electron Devices Meeting), 3 patents, 2 chapters and 1 editorial book (Nanocrystals in nonvolatile memory). In last 5 years, his research has been cited over 400 times with an h-index of 11 and i10-index of 13 (from Google Scholar citation report). His current research interests include the design, fabrication, characterization, and analysis of novel high-k and nanocrystals; design, fabrication, characterization, and analysis of RRAM, VRRAM, crossbar memory, storage class memory, high-density nanoscale 3D memory devices etc

Title: Three-dimensional integration of an emerging nonvolatile memory for the high-density and neuromorphic applications

Abstract: Due to scalability potential, low power applications, excellent reliability and cost effectiveness, resistive random-access memory (RRAM) devices have attracted considerable attention for potential application in the next generation emerging nonvolatile devices. Higher performances of RRAM devices are demonstrated in various types of binary oxide, transition metal oxides. Recently, several outstanding works significantly promote the RRAM devices for high-density and neuromorphic application with 3D vertical crossbar design. However, sneak leakage current can forcefully limit the performance of such 3D RRAM array. The typical leakage problem can overcome by nonlinear current at LRS or by using complementary resistive switching (CRS). Unfortunately, the common electrode of the CRS device can increase the process complexity and fabrication cost. Beside ultra-high-density memory applications, memristor devices have attracted considerable attention for the brain-inspired computing applications. Conventional computers based on Von Neumann architecture are not enough efficient to handle complex computation task, which only can be solved by a brain-inspired computing system.Although several attempts have made the progress in this particular field but the adoption of overall brain psychological phenomena by electronic synapses are somehow missing. Therefore, a proper understanding of psychological similarities between neuron behavior and memristor can provide an essential platform for the brain-inspired computing or neuromorphic computing. In this work, a TiOx/Al2O3-based 3D vertical hybrid RRAM will be discussed, which can show resistive switching (RS) performance and also the CRS mode of operation and useful for the high density and neuromorphic applications. The complete concept is divided into three parts. In 1st part, the TiO2/Al2O3- based 3D vertical RRAM devices are capable to show stable RS performances. The devices are showing nonlinear behavior at the low resistance state. The RS mechanism is confirmed by the high-resolution transmission electron microscopic (HRTEM) view of the formation of a clear conductive Ti5O9 nanofilament followed by a tunnel gap. The following 2nd part is presenting the realization of CRS mode of operation after the reset failure in the common-electrode-less TiO2/Al2O3-based 3D vertical RRAM devices. The switching mechanism of CRS is explained with the reference of HRTEM image of the Ti5O9 nanofilament in RS mode. Higher nonlinearity is achieved under CRS as compare to RS. This is the first work of the CRS operation along with RS operation in a complete 3D vertical hybrid RRAM structure. In 3rd part of this work, the behavioral and psychological emulation of synaptic activities by the TiOx/Al2O3-based electronic synaptic junction (ESJ) will be presented.